1. Field of the Disclosure
The present disclosure generally relates to the formation of semiconductor devices, and, more specifically, to various methods of forming contact structures for semiconductor devices and the resulting devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region. Irrespective of whether a planar or non-planar device is considered, electrical connections must be formed to the device so that it may operate as intended. That is, electrical connections must be made to the source region, the drain region and the gate electrode of the device.
By using such field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, embedded memories and the like. Over the recent years, due to the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density” (i.e., devices per area) in such products has been increased over the recent years. Such improvements in the performance of transistor devices has reached the point where the limiting factor of the finally achieved operating speed of complex integrated circuit products is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the device level, including the actual semiconductor-based circuit elements.
Typically, the conductive structures that actually make contact with the device itself, i.e., the source region, the drain region and the gate electrode, are referred to as “contacts” within the industry. Such conductive contacts are formed in one or more layers of insulating material. The entire arrangement of the conductive contacts and the associated layer(s) of insulating material are sometimes referred to as the “contact level” of the overall electrical “wiring arrangement” that is formed to provide electrical connection to the integrated circuit device. In some cases, the contact structure may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. In other cases, the contact structure may have an elongated line-type structure (e.g., so-called trench silicide structures for contacting to source/drain regions). The contact structures may be made of a variety of materials, such as tungsten, which, in combination with appropriate barrier materials, has proven to be a viable contact metal.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the contact level, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures include an appropriate metal and provide the electrical connection of the various stacked metallization layers. In some cases, the increased packing density mandated the use of sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits.
As device dimensions have decreased, e.g., transistors with gate lengths of 50 nm and less, the contact elements in the contact level have to be provided with critical dimensions in the same order of magnitude. When forming tungsten-based contact plug elements, typically the interlayer dielectric material is formed first and is patterned so as to receive contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. In particular, in densely packed device regions, the lateral size of the drain and source areas, and thus the available area for the contact regions, is 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy.
For this reason, contact technologies have been developed in which contact openings are formed in a self-aligned manner by removing dielectric material, such as silicon dioxide, selectively from the spaces between closely spaced gate electrode structures. That is, after completing the transistor structure, the sidewall spacer material and gate cap layer adjacent the gate electrode structures are used as etch masks for selectively removing the silicon dioxide material in order to expose the contact regions of the transistors, thereby providing self-aligned trenches that are substantially laterally delineated by the spacer structures. Consequently, a corresponding lithography process only needs to define a global contact opening above an active region, wherein the contact trenches then result from the selective etch process using the exposed portions of the sidewall spacer/gate cap layer as an etch mask. Thereafter, an appropriate contact material, such as tungsten and the like, may be filled into the contact trenches/openings.
Another problem with continued scaling of transistor devices is that the electrical resistance between the conductive contacts and the transistor element is becoming a larger portion of the overall electrical resistance. Traditionally, metal silicide layers are formed in the source/drain regions of a device and on the gate electrode of a device in order to reduce electrical contact resistance. Ideally, the contact area between the metal silicide layer and the underlying silicon or epi semiconductor material could simply be increased. In the case of FinFET devices, this could theoretically be accomplished by forming the epi material on the fins in an un-merged condition, i.e., no contact between epi material on adjacent fins, and thereafter forming an individual metal silicide layer that wraps around each of the separated epi materials. In practice, this is a very difficult task for several reasons. First, when epi semiconductor material is grown on a fin, it is very difficult to control the thickness of the epi semiconductor material. Thus, the epi material may unintentionally be merged together, thereby preventing the formation of the wrap-around metal silicide layers. One possible solution to avoid such unintended fin merger would be to form the epi material on the fin to a very small thickness to virtually assure that unintended fin merger does not occur. The drawbacks to this approach are that such a very small volume of epi material will tend to increase the overall resistance and such a thin layer of epi material may be substantially consumed by the metal silicide material and/or damaged during the contact formation process.
Fundamentally, in both FETs and FinFETs, the area available for establishing electrical contact to the devices, especially the source/drain regions, has been significantly reduced due to device scaling. This decrease in available contact area is the result of the reduced lateral distance between adjacent devices due to increased packing densities. All other things being equal, the reduction in the available contact area results in an undesirable increase in contact resistance, which results in the degradation of the performance of the device. The present disclosure is directed to various methods of forming contact regions for semiconductor devices and the resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.